1. Field of the Invention
The present invention relates to a storage system disposed with plural integrated circuits.
2. Description of the Related Art
A storage system is disposed with plural storage devices and a controller that accesses at least one storage device of the plural storage devices in accordance with an access request from a higher-level device. The controller is, for example, disposed with a cache memory that temporarily stores data that are to be written in the storage devices or are to be read from the storage devices, a microprocessor that controls the reading and writing of data with respect to the storage devices, an interface circuit (a higher-level adapter) with the higher-level device (e.g., a host computer or another storage system), an interface circuit (a lower-level adapter) with the storage devices, an interface circuit (a CM adapter) with respect to the cache memory, an interface circuit (an MP adapter) with respect to the microprocessor), and a switch circuit that is connected to the higher-level adapter, the lower-level adapter, the CM adapter and the MP adapter. Each of the aforementioned adapters and the switch circuit is an LSI (Large Scale Integration), and transmission and reception are performed between the LSIs. As the interface of transmission and reception between the LSIs, PCI-Express is employed.
In the LSIs, for example, there are disposed a transmission LSI component 101 shown in FIG. 1 and a reception LSI component 201 shown in FIG. 2.
In the transmission LSI component 101 (receiving LSI component 201), there are disposed a user logic 102 (202) and a PCI-Express interface circuit component 106 (206) that exists on a lower level. In the PCI-Express interface circuit component 106 (206), there are disposed plural logic circuits. Those logic circuits are, from a higher-level side to a lower-level side, a TL transmission logic 103 (TL reception logic 203) that performs processing by a TL (Transaction Layer), a DLL transmission logic 104 (DLL reception logic 204) that performs processing by a DLL (Data Link Layer), and a PL transmission logic 105 (PL reception logic 205) that performs processing by a PL (Physical Layer).
In PCI-Express, as packets handled by a TL (below, TLPs (Transaction Layer Packets), there are Posted-TLP that is a TLP of a type (Posted) that does not require a reply, Non-Posted TLP that is a TLP of a type (Non-Posted) that requires a reply, and Completion-TLP that is a TLP of a type (Completion) that represents a reply.
In the TL transmission logic 103 (TL reception logic 203), there are disposed three transmission buffers 1032, 1033 and 1034 (three reception buffers 2023, 2033 and 2034) that correspond to the three TLP types of Posted, Non-Posted and Completion, and a demultiplexer (below, DEMUX) 1031 (2031) is disposed in a higher level than those. Further, in the TL transmission logic 103, an MUX 1035 is disposed in a lower level of the three transmission buffers 1032, 1033 and 1034.
In the transmission source LSI, the TL transmission logic 103 performs the following (3-1) to (3-3):
(3-1) when the TLP that is to be transmitted is a Posted-TLP, the TL transmission logic 103 temporarily stores that TLP in the Posted transmission buffer 1032 and transmits the TLP from that buffer 1032 (S302, S303 and S306 in FIG. 3);
(3-2) when the TLP that is to be transmitted is a Non-Posted TLP, the TL transmission logic 103 temporarily stores that TLP in the Non-Posted transmission buffer 1033 and transmits the TLP from that buffer 1033 (S302, S304 and S306 in FIG. 3);
(3-3) when the TLP that is to be transmitted is a Completion-TLP, the TL transmission logic 103 temporarily stores that TLP in the Completion transmission buffer 1034 and transmits the TLP from that buffer 1034 (S302, S305 and S306 in FIG. 3).
In the reception source LSI, the TL reception logic 203 performs the following (4-1) to (4-3):
(4-1) when the TLP that has been received is a Posted-TLP, the TL reception logic 203 temporarily stores that TLP in the Posted reception buffer 2032 (S401, S402 and S403 in FIG. 4);
(4-2) when the TLP that has been received is a Non-Posted TLP, the TL reception logic 203 temporarily stores that TLP in the Non-Posted reception buffer 2033 (S401, S402 and S404 in FIG. 4);
(4-3) when the TLP that has been received is a Completion-TLP, the TL reception logic 203 temporarily stores that TLP in the Completion reception buffer 2034 (S401, S402 and S405 in FIG. 4).
As a technology that relates to transmission and reception by PCI-Express, the technology disclosed in JP-A-2006-189937, for example, is known. According to JP-A-2006-189937, buffer areas that correspond to the TLP types are allocated at a necessary timing from the buffers.